Abstract: In this research, a FinFET based methodology for the design of self timed adder is proposed which provides lesser power consumption when compared to CMOS. The FinFET based adder is designed to reduce the carry chain Propagation delay time. The adder is designed using double gate FinFET in 32nm technology. The Proposed design based on FinFET further reduces the second order effects which occur in CMOS based digital circuits below 65 nm technology. A Self Controlled Voltage Level (SVL) Circuit for the adder drastically reduces the standby power. The design also eliminates the short channel effects occurring in conventional CMOS circuits. Experiments were carried out on designing a FinFET based NAND logic gate using SVL technique and the performance is compared with the conventional CMOS based NAND gate. The proposed FinFET based self timed adder performance is compared with the existing conventional design. The power is reduced by 20% in the proposed design. Experimental results on the 32 nm predictive technology model for FinFET adder design demonstrate the effectiveness of the proposed optimization framework.
S. Saravanan and V.M. Senthil Kumar, 2016. Design of a Reduced Carry Chain Propagation Adder Using FinFET. Asian Journal of Information Technology, 15: 1670-1677.