Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 15
Page No. 2693 - 2698

Three State Skip Logic Built-In Self-Test Scheme for Combinational Circuits

Authors : S. Lokesh, O. UMA Maheswari and P. Sakthivel

Abstract: As technology processes scale up and design complexities grow, system-on-chip integration continues to rise rapidly. According to these trends, increasing test data volume is one of the biggest challenges in the testing industry. In this study, we propose a test data compression based Three State Skip (TSS) Logic for Low Power Built in Self Test (BIST) applications. The Three State Skip (TSS) primarily aims at reducing the switching activity during a scan by skipping preselected test vectors. For improving the compression efficiency, a Reconfigurable Johnson Counter (RJC) is used to reconfigure and skip function. It is useful to reuse previously used data for making present data by using the function of feedback or tapping of the Linear Feedback Shift Register (LFSR). Three State Skip circuit is developed to achieve little scan power by splitting and skipping long scan chain switching activities. This research solves the challenges faced in Fault detection circuits with the proposed Three State Skip logic. The Efficiency of such system is compared with Two Folded State Skip (TFSS) Logic and generates minimum test patterns by skipping the scan chain.

How to cite this article:

S. Lokesh, O. UMA Maheswari and P. Sakthivel, 2016. Three State Skip Logic Built-In Self-Test Scheme for Combinational Circuits. Asian Journal of Information Technology, 15: 2693-2698.

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