Abstract: This study proposes an innovative architecture for medium speed Finite Impulse Response (FIR) filter based on Distributed Arithmetic (DA). This architecture composed of linear systolic arrays is derived by a two factor decomposition of both the order of the filter and the length of the input sequence. Many variants of medium speed systolic structures are possible that depend on how the input word length is factored. The design metrics, used to verify the effectiveness of the proposed architecture are the delay elements, speed in terms of maximum frequency and area as the number of slices. This design is implemented on the Xilinx Virtex-6 Field Programmable Gate Array (FPGA). A comparison of the performance metrics is made among the variants of medium speed architectures. The simulation results of the proposed design for different filter taps when related to the existing low speed and high speed systolic architectures shows that it requires intermediate area resources, latency and results in a medium speed. The implementation results also distinctly exhibit that the proposed architecture requires less hardware resources and also yields remarkably higher maximum frequency for various filter orders when compared with an existing DA based medium speed FIR filter.
K.G. Shanthi, J. Faritha Banu, S. Sesha Vidhya and A. Manikandan, 2017. Flexible Medium Speed Systolic Architecture for FIR Filter Based on Distributed Arithmetic. Asian Journal of Information Technology, 16: 163-168.