Authors : Venkateshappa and P. Cyril Prasanna Raj
Abstract: Dual Tree Complex Discrete Wavelet Transform (DTCWT) decomposes input image into approximation and six detail sub-bands using row and column processing filter banks. Each filter comprising of 10 coefficients requires multipliers and adders that are twice larger than that of discrete wavelet transform computation. In this study, the computation complexity in DTCWT computation is reduced by considering the redundancy in filter coefficients. A multiplexer-demultiplexer based logic is designed to reduce the number of filters by 75%, a pipeline architecture is designed to reduce the number multipliers by 60% as compared with conventional DTCWT architecture. The designed architecture implemented on FPGA and the design operates at frequency of >200 MHz.
Venkateshappa and P. Cyril Prasanna Raj, 2017. FPGA Implementation of Area Efficient and High Throughput 2D DTCWT Architecture with Pipelined Scheme. Asian Journal of Information Technology, 16: 511-520.