Authors : Vishnu V. Nair and P.. Rajeswari
Abstract: Interfacing core logic and external world is always been a challenge in VLSI industry. Specially designed IO circuits are used for this purpose. Isolation of crucial core part is achieved by the help of IO circuitry. This study proposes a bi-directional IO for various loads depends on the core circuit which drives the IO. The driving capability of the IO circuit can be varied from 10-40 pF based on the loading in the pad. Control is provided by the help of signals produced by the core circuit. By varying these signals, the loading ability for an IO can be set by the internal logic. In this study, an IO is proposed to connect 1.2 V internal circuitry to 3.3 V pad. Pull-up pull-down networks are included to ensure low short circuit current.
Vishnu V. Nair and P.. Rajeswari, 2017. A 3.3 V Bi-Directional IO for Multiple Loads in 55 nm CMOS. Journal of Engineering and Applied Sciences, 12: 9554-9559.