Authors : E. Lakshmi Prasad, A.R. Reddy and M.N. Giri Prasad
Abstract: Network on chip is a modern architecture for multiprocessor. Due to the complex routing in Network on Chip (NoC), it is obstructed with the issue of latency, deadlock and traffic congestion. The problem of deadlock and traffic congestion can be managed by the proposed method called as Diagonal Virtual Channel Router (DVCR) design. Low latency XY routing algorithm can reduce latency to reach the critical path destination node in NoC. Therefore, DVCR and XYD routing algorithm can manage the congestion and latency can be reduced by 50% when compared to existing methods. These methods are examined for 4×4 2-D MESH and 2-D TORUS. Experimental research carried out by using Xilinx 14.7 and targeted on the Vertex-7 FPGA. As per the synthesis report, the minimum amount of time period to reach the critical path node in 2D-mesh is 5.548 nsec and for 2D-Torus is 5.507 nsec, so, each router can execute in four clock cycles, therefore, overall critical path distance node in 2D-mesh is 16.644 nsec and in 2D torus is 11.014 nsec. Low latency applications for NoC based MPSoCs.
E. Lakshmi Prasad, A.R. Reddy and M.N. Giri Prasad, 2018. DVCR: Diagonal Virtual Channel NoC Router Architecture for Multiprocessors. Journal of Engineering and Applied Sciences, 13: 3562-3566.