Authors : D. Khalandar Basha, Shashikanth Reddy and K. Aruna Manjusha
Abstract: SRAM is one of the basic element used in memory. Large memories are needed as more amount of information to store in today’s life. The on-chip memory is increasing for every generations of processors and systems. In VLSI design metrics are area, cost, portability, speed and power. To meet specification many topologies are existing for basic SRAM cell design. In this study basic 6T SRAM is considered for which additional transistors are added to reset the memory using reset pin. The back to back inverter circuit of SRAM is driven on both sides. For this circuit two additional transistors are added to enable based on row-sel and coln-sel inputs. To increase the speed of operation of the circuit additional circuit gate level body biasing circuit. This modified basic SRAM cell is used to design for 16×1 SRAM memory later extended for 16×8 memory. The circuit is designed with GPDK45 and simulated by cadence spectre simulator.
D. Khalandar Basha, Shashikanth Reddy and K. Aruna Manjusha, 2018. 2D Symmetric16×8 SRAM with Reset. Journal of Engineering and Applied Sciences, 13: 58-63.