Journal of Engineering and Applied Sciences

Year: 2018
Volume: 13
Issue: 8 SI
Page No. 6335 - 6340

Low Power Implementation of DTMF Chip by Using Power Gating Technique with Merge Flops

Authors : Anuradha Shankar, Srinivas Manchala and N. Mohan Kumar

Abstract: With the advent of technology and increasing concern for designing low power devices, systems with longer sustaining battery life are the demand. This study focuses on design of low power DTMF chip which is extensively used in telecommunication systems. Firstly, the existing techniques are implemented and compared with the power gating technique that results in reduction in leakage power consumption by 96% and the overall power consumption by 7% compared to the design without low power intent. The addition of low power cells in power gating technique results in an increase in area by 15% at the placement stage and a placement density >100% after routing. An algorithm is proposed to improve the efficiency of power gating by restricting the impact of this increase in area due to addition of low power cells by using merge flip-flops.

How to cite this article:

Anuradha Shankar, Srinivas Manchala and N. Mohan Kumar, 2018. Low Power Implementation of DTMF Chip by Using Power Gating Technique with Merge Flops. Journal of Engineering and Applied Sciences, 13: 6335-6340.

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