Abstract: This study presents a design and implementation of a direct digital frequency synthesizer based on Quarter Sine Wave. The RTL level simulation and gate level simulation of a proposed design is done by means of a Quartus-Model-Sim. This design is a digital part. The digital part consists of a Phase Accumulator (PA) and a Look up Table (LUT). The Phase Accumulator is implemented by means of a register along with an adder and feedback loop. LUT is implemented using verilog code. The size of LUT is reducing by storing quarter of sine wave in the ROM. This design was tested with various tuning frequencies and the result shows that the output frequency is directly proportional to the tuning input frequency.
A.A. Alsharef, M.A. Mohd. Ali and H. Sanusi, 2012. Direct Digital Frequency Synthesizer Design and Implementation on FPGA. Research Journal of Applied Sciences, 7: 387-390.