Abstract: Multiplication is the fundamental function in most of the lightweight systems. In most of the signal processing applications, the demand for low cost multiplier is the major concern. This research different multiplier algorithms like Urdhava Tiryagbhyam and Anurupye; it investigates the implementation of low pass Finite Impulse Response (FIR) filter. The functional unit of 8 bit multiplier and FIR filter is described using VHDL, simulated and synthesized for both FPGA and ASIC CMOS (180 and 90 nm) technology are reported in this research the implementation of Anurupye algorithm ensures the reduction of area and leakage power in comparison with Urdhava Tiryagbhyam architectures. The functionality of these circuits was checked in Xilinx Spartan6 XC6SLX45T-2CSG324 FPGA device and a number of lookup tables, delay was calculated.
R. Deepa and S. Elango, 2018. Implementation of Low Area FIR Filters Using Vedic Multiplication Algorithms. Journal of Engineering and Applied Sciences, 13: 4733-4738.