Asian Journal of Information Technology

Year: 2005
Volume: 4
Issue: 8
Page No. 768 - 772

Low-Power Pipeline FFT Processor with Area-efficient Multipliers

Authors : Jung-Yeol Oh , Kwang-Ho Chun and Myoung-Seob Lim

Abstract: Presented here a new efficient pipeline FFT(Fast Fourier Transform) architecture based on the radix-2 4 algorithm. The pipeline architecture with the new algorithm has the same number of multipliers as that of the radix-2 2 algorithm. However, the multiplier complexity could be reduced by an amount of above 30% by means of replacing a half of programmable multipliers with the newly proposed constant multipliers. A newly proposed complex constant multipliers can enhance the area/power efficiency of the design. From synthesis simulations, the proposed complex constant multiplier achieved above 60% area reduction compared with the conventional programmable multiplier.

How to cite this article:

Jung-Yeol Oh , Kwang-Ho Chun and Myoung-Seob Lim , 2005. Low-Power Pipeline FFT Processor with Area-efficient Multipliers . Asian Journal of Information Technology, 4: 768-772.

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