Authors : Mohammad Shakeri, Md. Mamun, Labonnah F. Rahman and Fazida Hanim Hashim
Abstract: Designing the low power devices are becoming very important field of research due to the increment of the number of portable devices. In this research, 16-bits shift register circuit design method is proposed using Single Edge Triggered (SET) D-Flip-flop. Moreover, a comparison study between the conventional circuit design and modified design is presented. The proposed circuit is designed using CEDEC 0.18 μm CMOS process. The simulated results show that SET D-FF circuit required lower power than the conventional shift register circuit. However, the conventional circuit required 16-transistors and the proposed design required 10-transistors. Therefore, 10-transistors SET D-flip-flop is the better option for 16-bits shift register.
Mohammad Shakeri, Md. Mamun, Labonnah F. Rahman and Fazida Hanim Hashim, 2013. Design and Optimization of the Power Consumption in 16-bits Shift Register Using Single Edge Triggered D-Flip-Flop. Journal of Engineering and Applied Sciences, 8: 38-43.