Authors : Jamshid M. Basheer and V. Murugesh
Abstract: Noise reduction in images or signals is the important process in image processing and signal processing applications. Most of the cases, filter is used to eliminate the noise in the images. Different filters are available in the image processing for noise reduction. In this study designed a 19-tap low pass FIR with reduced MAC unit. The filter is efficiently designed by using MATLAB Simulink and Xilinx system generator. Reduced MAC unit reduces the hardware utilization of the device. The noisy input signal is applied into the filter for noise elimination. After the completing the Simulink simulation, start to generating the verilog HDL code using Xilinx system generator. In the time of code generation the device specifications are selected for Field Programmable Gate Array (FPGA) implementation. System generator is used to implement the filter into the FPGA hardware. The device utilization and timing summary of the filter can be evaluated using Xilinx 12.4 simulation tool.
Jamshid M. Basheer and V. Murugesh, 2017. Design of Low Pass FIR Filter for FPGA Implementation Using Xilinx System Generator. Journal of Engineering and Applied Sciences, 12: 9121-9125.