Abstract: The desire in this research is to design a Mealy state digital machine using NAND gates only to compute the GCD of any two numbers. In the design, state selection, input variable, output variable definition and output assignment to ensure accurate result are considered. The method employed in this design is a classical method of digital design that utilized purely the State diagram, State Table, Excitation Table and Kanaugh Map (K-Map). The GCD of the numbers (40, 24) was obtained as 8. Although, the machine is capable of computing the GCD of any number provided the input is stated correctly.

INTRODUCTION

A state digital machine transverses through a predetermined sequence of the state in an order fashion. A state is a set of values measured at different part of circuits. The digital machine designs are widely used for sequential control logic which forms the core of many digital systems (Papadinatou and Sarma, 1972), a state digital machine are required in a variety of applications covering a broad range of performance and complexity low level controls of microprocessor in VLSI peripheral interfaces, bus arbitration and timing generation in conventional microprocessor, custom bit slice microprocessor, data encryption and decryption and transmission protocol are but a few example (Hill and Peterson, 1997).

Typically, the details of control logic are the last to settle in the design circle, since they are continuously affected by changing system requirements and feature enhancement; programmable logic is a forgiving solution for control logic design because it allows easy modification to be made without disturbing PC board layout. Its flexibility provides an escape valve that permits design changes without impacting time market.

They are basically two methods of designing the state digital machine viz one hot method and classical method. In this research, classical method of design was chosen to design Mealy state machine to avoid erratic operation of circuitry driven by the state machine. The state machine architectures are shown in the Fig. 1.

Fig. 1:	Modified mealy digital machine

State diagram: State diagram allows the designer to describe the desired state machine operation graphically. This help to visualize the operation of the state machine prior to its implementation because it contains wealthy informations. The Fig. 1 shows state transition, the circles and the arrows describe, how the state machine moves from one state another. The circles represents a particular value of state variable, the arrows lines describe how the state machine transitions to the next state and arrow lines also contain the Boolean expression, which shows the criteria for a transition from one state to another. If the Boolean expression is true and the current state is the state at the source of the arrow line then the state machine will transit to the destination state on the clock (Fig. 2).

Input variable: All input variables were made to be synchronized to the state machine clock. If they are not, strange things will begin to happen in the actual operation (illegal state will be mysteriously entered), this could lead to total state machine lockup.

Fig. 2:	State diagram of the Mealy digital machine (GCD) realize

Inevitably, the design will fail intermittently in the field (Hallbaueyer, 1998), this is because of the fact that a physical state machine implementation uses physical gates, which have non zero propagation delay. An input signal propagates through the gates to the D input of one state flip flop will slightly faster or slower than the same input signal travelling through a different set of gates to another flip flop’s D input.

Output variable definition: The verilog is used to define statement to associate a state value to each name (Armstrong, 1962). We simply transformed the data directly from the state diagram. The state name and the state value are inside the circle that define each state as:

Output assignment section: Continuous assignment is used to assign an output to its associated state bit, this continuous assignment will synchronize to a zero delay wire i.e., the output name and the registered bit are synonyms. If there are asynchronous inputs to the state machine; this is a good stage to instantiate synchronizer (Kohavi, 2001; Barthel, 2004).

Design method: This design utilized classical method of design using purely State Table, Excitation Table and K-Maps that describes the D flip flop characteristics equations. The following procedures/methods were taken into consideration.

Method I: The State Table that defines the control unit of the GCD processor is developed, where, S = 00, S1 = 01, S2 = 10 and S3 = 11 presenting digital codes in binary form.

Method II: The Excitation Table developed from the State Table in method II is as:

Method III: K-Map was employed to develop the Boolean expression of the Sum Of Product (SOP). As in case I:

Case I: Map for D₁⁺

(1)

Case II: Map for D₀⁺

(2)

Similarly the following were obtained in the same manner:

(3)

(4)

(5)

(6)

(7)

To realize the GCD all the Boolean expression has converted to NANDs as follows (Almaini et al., 1980; Lee and Davidson, 2005; Dietmeyer, 1999):

(8)

(9)

(10)

(11)

(12)

(13)

(14)

The logic circuit of Mealy digital machine was realized using the Boolean expression from (8-14) as depicted in Fig. 3.

The following hardware language was used to instruct the machine to compute the GCD of (40, 24) (Shahdad, 1986; Shiva, 2005).

Fig. 3:	Computed Mealy digital state machine