Asian Journal of Information Technology

Year: 2016
Volume: 15
Issue: 2
Page No. 277 - 282

Performance Analysis of Low Power Port Bandwidth Weight Router Architecture

Authors : M. Deivakani and D. Shanthi

References

Al Faruque, M.A., T. Ebi and J. Henkel, 2012. AdNoC: Runtime adaptive network-on-chip architecture. IEEE Trans. Very Large Scale Integr. Syst., 20: 257-269.
CrossRef  |  

Banerjee, A., P.T. Wolkotte, R.D. Mullins, S.W. Moore and G.J.M. Smit, 2009. An energy and performance exploration of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. Syst., 17: 319-329.
CrossRef  |  

Elghazali, M., A. Elhossini and S. Areibi, 2009. HW/SW co-design architecture exploration for VLSI maze routing. Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2009 CCECE'09, May 3-6, 2009, IEEE, St. John's, NL, pp: 1188-1193.

Gester, M., D. Muller, T. Nieberg, C. Panten and C. Schulte et al., 2012. Algorithms and data structures for fast and good VLSI routing. Proceedings of the 49th Conference on Annual Design Automation, June 3-7, 2012, ACM, New York, USA., ISBN: 978-1-4503-1199-1, pp: 459-464.

Mattihalli, C., S. Ron and N. Kolla, 2012. VLSI based robust router architecture. Proceedings of the 2012 Third International Conference on Intelligent Systems, Modelling and Simulation (ISMS), February 8-10, 2012, IEEE, Kota Kinabalu, Malaysia, pp: 43-48.

Md-Yusof, Z., M.K. Hani, M.N. Marsono and N.S. Husin, 2009. Optimizing multi-constraint VLSI interconnect routing. Proceedings of the 2009 12th International Symposium on Integrated Circuits, ISIC'09, December 14-16, 2009, IEEE, Singapore, Asia, pp: 655-658.

Pham, P.H., J. Song, J. Park and C. Kim, 2013. Design and implementation of an on-chip permutation network for multiprocessor system-on-chip. Very Large Scale Integr. Syst. IEEE. Trans., 21: 173-177.
CrossRef  |  Direct Link  |  

Roy, D. and P. Ghosal, 2013. A fuzzified approach towards global routing in VLSI layout design. Proceedings of the 2013 IEEE International Conference on Fuzzy Systems (FUZZ), July 7-10, 2013, IEEE, Hyderabad, India, pp: 1-8.

Shacham, A., K. Bergman and L.P. Carloni, 2008. Photonic networks-on-chip for future generations of chip multiprocessors. Comput. IEEE. Trans., 57: 1246-1260.
CrossRef  |  Direct Link  |  

Vangal, S.R., J. Howard, G. Ruhl, S. Dighe and H. Wilson et al., 2008. An 80-tile sub-100-w teraflops processor in 65-nm cmos. Solid State Circuits IEEE. J., 43: 29-41.
CrossRef  |  Direct Link  |  

Design and power by Medwell Web Development Team. © Medwell Publishing 2024 All Rights Reserved