References

Choi, P., S.C. Shin and J.G. Chung, 2000. Efficient ROM size reduction for distributed arithmetic. Proceedings of the IEEE International Symposium on Circuits and Systems, May 28-31, 2000, IEEE, Geneva, Switzerland, ISBN:0-7803-5482-6, pp: 61-64.

Eshtawie, A.M. and M. Othman, 2007. An algorithm proposed for FIR filter coefficients representation. Intl. J. Appl. Math. Comput. Sci., 4: 24-30.

Kung, H.T., 1982. Why systolic architectures. IEEE. Comput., 15: 37-45.

Meher, P.K., 2006. Hardware-efficient systolization of DA-based calculation of finite digital convolution. Circ. Syst. II: IEEE Trans. Exp. Briefs, 53: 707-711.
CrossRef  |  Direct Link  |  

Meher, P.K., S. Chandrasekaran and A. Amira, 2008. FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process, 56: 3009-3017.
CrossRef  |  Direct Link  |  

Mohanty, B.K. and P.K. Meher, 1996. Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters. IEEE. Proc. Comput. Digital Tech., 143: 436-439.
CrossRef  |  Direct Link  |  

Parhi, K.K., 1999. VLSI Digital Signal Processing Systems: Design and Implementation. 2nd Edn., Wiley-Interscience Publication, New York, USA., ISBN-13: 9780471241867, Pages: 784.

Proakis, J. and D. Manolakis, 1996. Digital Signal Processing: Principles, Algorithms and Applications. Prentice-Hall, Englewood Cliffs, New Jersey, USA.

Shanthi, K.G. and N. Nagarajan, 2013. Memory based hardware efficient implementation of FIR Filters. Int. Rev. Comput. Software, 8: 1718-1733.
Direct Link  |  

Shanthi, K.G. and N. Nagarajan, 2014. High speed and area efficient FPGA implementation of FIR filter using distributed arithmetic. J. Theoret. Appl. Inf. Technol., 62: 627-633.
Direct Link  |  

Shanthi, K.G. and N. Nagarajan, 2015. Area-efficient and low latency architecture for high speed fir filter using distributed arithmetic. ICIC Express Lett. Part B Applic. Int. J. Res. Surv., 6: 2053-2058.

Shanthi, K.G., N. Nagarajan and C. Kalieswari, 2014. FPGA realization of high speed FIR filter based on distributed arithmetic. Int. J. Eng. Technol., 6: 1407-1414.
Direct Link  |  

Sudhakar, V., N.S. Murthy and L. Anjaneyulu, 2012. Area efficient pipelined architecture for realization of FIR filter using distributed arithmetic. Proceedings of the International Conference on Industrial and Intelligent Information, October 7-12, 2012, IACSIT Press, Singapore, pp: 169-173.

White, S.A., 1989. Applications of the distributed arithmetic to digital signal processing: A tutorial review. IEEE. ASSP. Mag., 6: 4-19.
CrossRef  |  Direct Link  |  

Yoo, H. and D.V. Anderson, 2005. Hardware efficient distributed arithmetic architecture for high-order digital filters. Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing Vol. 5, March 23-23, 2005, IEEE, Philadelphia, Pennsylvania, ISBN:0-7803-8874-7, pp: 125-128.