References

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Kim, C.H. and K. Roy, 2002. Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors. Proceedings of the International Symposium on Presented Low Power Electronics and Design, August 12-14, 2002, Purdue University, West Lafayette, Indiana, pp: 1-4.

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Taco, R., M. Lanuzza and D. Albano, 2015. Ultra-low-voltage self-body biasing scheme and its application to basic arithmetic circuits. VLSI Des., 2015: 1-10.
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Yadav, S., N. Malik, A. Gupta and S. Rajput, 2013. Low power SRAM design with reduced read/write time. Intl. J. Inf. Comput. Technol., 3: 195-200.
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