References

Bousamra, A., A.K. Jones and R. Melhem, 2012. Codesign of NoC and cache organization for reducing access latency in chip multiprocessors. IEEE. Trans. Parallel Distrib. Syst., 23: 1038-1046.
CrossRef  |  Direct Link  |  

Grot, B., J. Hestness, S.W. Keckler and O. Mutlu, 2009. Express cube topologies for on-chip interconnects. Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture HPCA 2009, February 14-18, 2009, IEEE, Raleigh, North Carolina, USA., ISBN:978-1-4244-2932-5, pp: 163-174.

Kumar, A., L.S. Peh, P. Kundu and N.K. Jha, 2007. Express virtual channels: Towards the ideal interconnection fabric. ACM. SIGARCH. Comput. Archit. News., 35: 150-161.
CrossRef  |  Direct Link  |  

Modarressi, M., A. Tavakkol and H. Sarbazi-Azad, 2010. Virtual point-to-point connections for NoCs. IEEE. Trans. Comput. Aided Des. Integr. Circuits Syst., 29: 855-868.
CrossRef  |  Direct Link  |  

Postman, J., T. Krishna, C. Edmonds, L.S. Peh and P. Chiang, 2013. Swift: A low-power network-on-chip implementing the token flow control router architecture with swing-reduced interconnects. IEEE. Trans. Very Large Scale Integr. Syst., 21: 1432-1446.
CrossRef  |  Direct Link  |  

Prasad, E.L., A.R. Reddy and M.G. Prasad, 2016. EFASBRAN: Error free adaptive shared buffer router architecture for network on chip. Procedia Comput. Sci., 89: 261-270.
Direct Link  |  

Prasad, E.L., A.R. Reddy and M.G. Prasad, 2016. Performance comparison of network on chip methods. Proceedings of the Online International Conference on Green Engineering and Technologies (IC-GET), November 19, 2016, IEEE, Coimbatore, India, ISBN:978-1-5090-4557-0, pp: 1-8.

Prasad, E.L., V. Sivasankaran and V. Nagarajan, 2011. Multiple task migration in mesh network on chips over virtual point-to-point connections. Intl. J. Comput. Intell. Inf., 1: 202-207.
Direct Link  |